FIG. 1 shows an example of an information processing apparatus. An information processing apparatus 1 includes a central processing unit (CPU) 11, a memory controller 12, a cache memory 13, a flash memory controller 14, a flash memory 15, a power supply unit 21, and a backup power supply unit 22, which are connected as shown in FIG. 1. As indicated by a solid line arrow, the power supply unit 21 to which AC power is provided supplies a DC power source voltage to power feeding targets 11, 12, 13, 14 and 15 shown enclosed by a short dashed line in FIG. 1. The backup power supply unit 22 is formed by, for example, a capacitor called a supercapacitor. The backup power supply unit 22 is charged by the DC power source voltage supplied from the power supply unit 21 while the power supply unit 21 is normally operating. During a power failure of the AC power source, or the like, the power supply unit 21 does not supply a DC power source voltage since an AC power source voltage is not supplied to the power supply unit 21. When the power supply unit 21 does not supply a DC power source voltage, the backup power supply unit 22 detects power failure and supplies a DC power source voltage to the power feeding targets 11, 12, 13, 14 and 15, as indicated by a dashed line arrow.
In this example, in order to enable data backup with two systems, two flash memories 15 are provided. For this reason, the flash memory controller 14 includes two direct memory access (DMA) engines (or DMA controllers (DMACs)) 141, and a defective block management table 142. The defective block management table 142 has stored therein information regarding defective blocks of the flash memory 15, and is referred to when the DMA engine 141 performs data backup. The DMA engine 141 recognizes a defective block (or a defective area) in the flash memory 15 by referring to the defective block management table 142 so as to identify an accessible block (or accessible area) of the flash memory 15, and performs backup of data for the accessible block.
During a power failure, since the supply of the DC power source voltage is performed from the backup power supply unit 22, there is a time limit on a backup process for data stored in the cache memory 13 that is a volatile memory. Therefore, in order to write the data of the cache memory 13 in the flash memory 15, data is written in parallel in two flash memories 15 that are non-volatile memories by using DMA engines 141 of two systems. However, when a difference occurs in the data backup time of the two systems due to an occurrence of an error, the data backup process is not completed unless the data backup by the slower system is completed. Furthermore, in a case where the data backup by the slower system cannot satisfy a time limit of the backup process, the data backup process fails.
Examples of an occurrence of an error include a case in which a block of the flash memory 15 to which data is transferred is recognized as a defective block by the defective block management table 142 when performing data backup, a case in which an error is detected when data is written to the flash memory 15, and other cases. When such an error occurs, a replacement process for searching for a block (or area) in a data-transferable, accessible in other words, flash memory 15 by referring to the defective block management table 142 becomes necessary.
FIG. 2 shows a data backup method of a related art. Before DMA transfer is started, the firmware of the information processing apparatus 1 causes the CPU 11 to specify, for each DMA engine 141, the beginning address of the cache memory 13 and the total data size to be transferred from the cache memory 13 to the flash memory 15. For example, the total data size is 2 Gbits, and the DMA transfer can be performed in units of 2 Mbytes. Control information necessary for a backup process is attached in units of each transfer and therefore, the transfer unit of the data to be actually transferred is 2×718 Mbytes.
In FIG. 2 and in FIG. 3 (to be described later), two flash memories 15 are denoted by Flash#0 and Flash#1 in such a manner as to correspond to the DMA engines 141 of two systems DMA0 and DMA1. In each of the systems DMA0 and DMA1, 1 Gbits of data, which is half of the total data size, is backed up.
In a case where backed-up data is to be read from the flash memory 15, the beginning address of the cache memory 13 and the total data size to be transferred from the flash memory 15 to the cache memory 13 are specified from the firmware to each of the DMA engines 141.
FIG. 3 shows a data backup method of the related art in a case where an error occurs. For the DMA engines 141, since the same data size is specified, the data backup by the system in which more errors occur during DMA transfer takes a longer time than data backup by the other system. For this reason, variations occur in the completion time of the data backup. For example, in a case where many errors occur in the system DMA0 and data backup takes a longer time, and errors scarcely occur in the system DMA1 and data backup is completed earlier, the data backup process for the information processing apparatus 1 is completed when the data backup by the system DMA0 is completed. In FIG. 3, as an example, in the data backup by the system DMA0, an error occurs between the backup of data D1-1 and the backup of data D1-2. On the other hand, in the data backup by the system DMA1, data D2-1 to D2-4 has been backed up without causing an error.
As described above, in the data backup method of the related art, problems exist including due to a case when data backup time periods of plural systems differ, the data backup process is not completed unless the data backup by the slowest system is completed.